|Basejump||ASIC Clouds||Celerity||Dark Silicon||Vision/ML Benchmarks||Bitcoin||GreenDroid||Kremlin|
The people that will succeed best in the Bespoke Silicon Group are those who love to build agressive but elegant systems and tune their performance or energy efficiency -- computers, compilers, graphics renderers, simulators, computers, neural networks, dynamic translation emulators, operating systems, boards, or even chips. They like coding or designing things, have done a lot of it, and know how to do solid, elegant designs, and don't mind explaining to others how to do it -- and maybe have worked at companies on software systems or chip design. They tend to have lots of little side projects and experiments that they have done outside of class. They might enjoy reverse-engineering things as well. Don't worry if you don't know all of these things; you will learn when you join the group!
Newsflash: Two BSG veterans finished their tour of duty at Google and are CEO and CTO of a new startup, Moloco, in Silicon Valley, which is applying machine learning to apps on mobile. Donghwan and Ikkjin were key contributors to the San Diego Vision Benchmark suite, which integrated a number of machine learning techniques. They also explored aspects of machine learning applied to compiler, and comp arch. Moloco is now valued at > $1B.
|June 2021||Congrats to Shashank and Sripathi for executing stellar MS theses. They are headed to the ML startup SambaNova!|
|May 2021||Congratulations to Emily and Xingyao on their respective ISCA papers on GraphIt for HammerBlade and on LSTM optimization.|
|2020||Huge Congrats to Nathan and Moein for completing their PhD's (the last two from UC San Diego)!|
|Winter 2019||Our BaseJump STL is now being used as one of the standard tests for open source SystemVerilog parser implementations! See this link for a description, and this link for results. BaseJump is a nice balance of not being impossible but also pushing the envelope. We are excited to be part of the movement to push greater SystemVerilog standardization and use.|
|Summer 2019||Our ASIC Cloud paper was selected for ACM Highlights! On average, only two papers per year out of all of computer architecture are selected for ACM highlights .|
|July 2019||We taped out two chips -- the HammerBlade Open Source GPGPU chip, and the BlackParrot Open Source RISC-V Multicore -- in 12 nm Global Foundries Technology on the same day. These are going to be two of the most awesome chips ever taped out in academia. We are super excited to see silicon come back! To our knowledge we are the first university in the world to use this technology.|
|May 2018||Released first version of Luis Vega's excellent Amazon F1 Accelerator Tutorial.|
|Sept 2017||BSG has relocated its World HQ from San Diego to Seattle!
So long and thanks for the fish (tacos), San Diego!
Of course we have many great memories.
|Aug 2017||Our team presented the Celerity 16nm chip, which had 5 Linux-capable RISC-V cores, a manycore array of 496 cores, and a binarized neural network at Hotchips. This work was joint with Cornell and Michigan. Taylor BSG did the front-end design of the SoC (i.e. the RTL) with the exception of the neural network, which was done by Cornell. All three teams contributed to Backend physical design, with Michigan leading!
|June 2017||The IEEE Micro 2017 Top Picks Issue ASIC Cloud Paper appears. If you haven't read one of our ASIC Cloud papers recently, read this one for a great overview!|
|April 2017|| Moein remotely presents Moonwalk ASIC Cloud NRE paper at ASPLOS 2017. |
Congrats Moein on a job well done!!
|Feb 2017||ASIC Cloud paper selected for Top Picks!|
|Jan 2017||ASPLOS NRE and ASIC Cloud paper in on first shot!|
|Aug 2016||Taylor BSG has released the ROCC Doc V2, which describes the Berkeley Rocket ROCC interface. Great work, Anuj!|
|June 2016||Group beer:|
|Mar 2016|| ISCA paper is in on first shot!
ASIC Clouds are going to rock your world, folks.
Congrats, Ikuo, Moein, and Luis!
|Jan 2016||CGO BlackBox paper is accepted. Congrats Byron and Brian!|
|Sep 2015||Teaser video of DoubleTrouble v1 board talking over FMC by Luis.|
|May 2015|| Lu passes his research exam with aplomb. Beer is consumed! |
A proud tradition: everybody in Taylor group
has passed the CSE research exam on the first try.
|Jan 2015||Double Trouble board comes back from assembly, and passes initial JTAG.|
|Nov 2014|| Double Trouble PC Board arrives back from the fab!|
We will use this to emulate our chips!
|Oct 2014||Welcome Ikuo and Shengye to Taylor BSG!|
|Aug 2014||Shelby Thomas, Enrico Tanuwidjaja, Gautam Akiwate, and Chetan Gohkale get their paper on CortexSuite into IISWC. Congrats guys!|
|June 2014|| Our UCSD BGA package arrives back from the fab!|
This thing is a scorching fast platform for our chips!
We are one of only several academic research groups in the US that has designed a BGA package in-house!
|June 2014||Taylor serves on DAC 2014 panel on future of HW for computer vision, next to Andrew Ng!|
|April 2014||Taylor gives a talk at DATE 2014 on dark silicon!|
|Mar 2014||Qiaoshi's paper appears in TECS. Congratulations, Qiaoshi!|
|Dec 2013||Anshuman's paper gets into ISPASS 2014 -- way to go Anshuman!|
|Nov 2013||Taylor group has first annual Thanksgiving feast!|
|Sep 2013||New PhD students joining BSG: Welcome, Michael, Moein, and Xiaochu!|
|Sep 2013||Jack Sampson joins Penn State as an Assistant Professor, and Saturnino Garcia to join University of San Diego as an Assistant Professor!|
|Sep 2013||Ashuman successfully defended his thesis, bringing BSG PhDs to 5! Way to go Anshuman!|
|June 2013||Anshuman's paper on Dynamically Reconfigurable Static NUCA Caches accepted at ICCD! Way to go, Anshuman!|
|Oct 2012||CGO Paper on Vector Shadow Memory accepted!|
|April 2013||Anshuman's paper on Time Cube accepted at SAMOS! Way to go, Anshuman!|
|April 2012||Anshuman wins best poster across our entire CSE department (best out of 38 posters) at the Jacobs School of Engineering Research Expo! Anshuman continues a group tradition started by DJ and Sat last year, when they won best poster (what are the odds?!). Way to go Anshuman!|
|Feb 2012||Submit to the Dark Silicon Workshop, DaSi:|
by Apr 2.
|Aug 2011||GreenDroid QsCores paper accepted into MICRO! Congrats, Ganesh|
|June 2011||NSF funds BSG to support prototyping efforts!|
|June 2011||OOPSLA paper accepted! Congrats to DJ, Sat, and Chris!|
|May 2011||FPL paper accepted! Congrats to Jack and Manish!|
|May 2011||Our student, Dr. Ganesh Venkatesh, successfully defends his thesis against 5 UC professors! Ganesh will be joining Intel Research.|
|April 2011|| Kremlin wins best Computer Science & Engineering poster |
(out of 40 posters!) at the Jacobs School of Engineering Research Expo!
|March 2011||Parkour paper accepted into HOTPAR. Awesome work DJ!|
|April 2011||Invited talk on Conservation Cores and GreenDroid at LCTES!|
|March 2011||C-cores for FPGAs paper accepted into FCCM. Way to go Manish!|
|Feb 2011||Kremlin paper accepted into PLDI!|
|Feb 2011||Kremlin wins best student poster in PPoPP 2011!|
|Nov 2010||HPCA paper on ECOcores (cores with Extreme CISC Operators) accepted.|
|Sept 2010||Dr. Swanson and I have minted our first PhD student: Dr Jack Sampson! Jack will be continuing with us as a postdoc so he can shephard some of his pending papers out to the presses!|
|Oct 2010||NSF funds BSG for $376K to attack issues in multicore programmability!|
|March 2010|| Our student, Jack Sampson, gives an awesome talk on the Conservation Cores paper at ASPLOS! |
|March 2010|| Our paper, Bridging the Parallelization Gap: Automating Parallelism Discovery and Planning,
was accepted into HOTPAR 2010.|
|Oct 2009||BSG wunderkind Sravanthi Kota Venkata presents our IISWC paper on the San Diego Vision Benchmark Suite in Austin, TX.|
|Sept 2009||Awarded 150,000 hours of compute time on the San Diego Super Computer TRITON Cluster for the Photon manycore compiler project!|
|Sept 2009||Nathan Goulding, Jonathan Babb, and I recently pulled two all-nighters in a row and designed a low-power prototype chip, called the C-core I, which will be the basis for processor designs in future fabrication regimes in which energy is limited by the utilization wall.|
CortexSuite, a benchmark for the emerging synthetic brain application (e.g. Machine Learning and Vision) domain, written in C.
It's available at cortexsuite.org.
The San Diego Vision Benchmark Suite, a benchmark for the vision application domain, written in MATLAB and clean C.
It's available at bsg.ai/vision.
|CODE GENERATION AND OPTIMIZATION OF GRAPH PROGRAMS ON A MANYCORE ARCHITECTURE|
PhD Thesis by Emily Furst, 2021.
|ParrotPiton and ZynqParrot: FPGA Enablements for the BlackParrot RISC-V Processor|
Master's Thesis by Shashank Vijaya Ranga, 2021.
|TinyParrot: An Integration-Optimized Linux-Capable Host Multicore|
Master's Thesis by Sripathi Muralitharan, 2021.
|Reducing the development cost of customized cloud infrastructure|
PhD Dissertation by Moein Khazraee, 2020.
|Specialization as a Candle in the Dark Silicon Regime|
PhD Dissertation by Nathan Goulding-Hotta, 2020.
|Caches for Complex Open Source System-on-Chip Designs|
Master's Thesis by Dai Cheol Jung, 2019.
|ArCuS: An Architecture for ASIC Cloud based Servers |
Master's Thesis by Pulkit Bhatnagar, 2017.
| Exploring Energy and Scalability in Coprocessor-Dominated Architectures for Dark Silicon Regime |
PhD Dissertation by Qiaoshi Zheng, 2015.
| Software and Hardware Techniques for Attacking the Multicore Interference Problem|
PhD Dissertation, by Anshuman Gupta, 2013.
| The Arsenal Tool Chain for the
GreenDroid Mobile Application Processor|
Master's Thesis, by Fei Jia, 2013.
| Parallel Speedup Estimates for Serial Programs|
PhD Dissertation, by Donghwan Jeon, 2012.
| A Practical Oracle for Sequential Code Parallelization
PhD Dissertation, by Saturnino Garcia, 2012.
| Configurable Energy-Efficient Co-processors to Scale the Utilization Wall|
PhD Dissertation, by Ganesh Venkatesh, 2011.
| Efficient Cache-Coherent Migration for Heterogeneous Coprocessors in Dark Silicon Limited Technology|
Master's Thesis, by Scott Ricketts, 2011.
| Design and Architecture of Automatically-generated Energy-reducing Coprocessors|
PhD Dissertation, by John Sampson, 2010.
| ASIC life extension through hardware patch interfaces|
Master's Thesis, by Slavik Bryksin, 2009.
| A Portable MATLAB Front-end for Tiled Microprocessors|
Master's Thesis, by Hyojin Sung, 2009.
| Genetic Compilation for Tiled Microprocessors|
Master's Thesis, by Jin Seok Lee, 2007.
| Memory Prefetching for the GreenDroid Microprocessor|
Master's Project, by David Curran, 2012.
| Extending an on-chip mesh network
off the chip|
Master's Project, by Joe Auricchio, 2011.
| Improving Hierarchical Critical Path Analysis Performance
Master's Project, by Chris Louie, 2011.
A tool for deionization, which enables
application embedding and improved benchmark precision.
Papers by topic...